1. Field of the Invention
The invention relates to a semiconductor device including a logic circuit or a logic gate. Particularly, the invention relates to a semiconductor device capable of reducing power consumption in a standby state.
2. Description of Related Art
Regarding memories such as flash memories and dynamic memories etc., according to demands of large capacity, low price and low power consumption, and small size fabrication steps thereof are also required to be simplified. In order to implement the above demands, some side effects are produced, for example, in fabrication of a single layer of polysillicon, increase of a threshold of a P-channel metal oxide semiconductor transistor may cause a side effect that a high-speed operation is hard to be implemented. Therefore, to mitigate the above problem, a transistor with a low threshold is added. However, when the threshold is reduced, even if a voltage Vgs between a gate and a source of the transistor is 0V, a phenomenon of leakage current still exists, which may cause extra power consumption. Generally, the smaller the threshold is, the larger the leakage current is, and the more obvious the power consumption is.
According to a disclosure of Japan Patent No. 2004-147175, a gate oxide film power switching transistor is disposed between a gate oxide film logic gate with a low threshold and a power line, and in a standby state, a relatively large inverse bias is applied on the power switching transistor, so as to reduce the leakage current of the power switching transistor.
FIG. 1 is a schematic diagram of a conventional circuit for reducing a leakage current. The circuit is adapted to a clock synchronous data transmission circuit such as an input output data buffer, etc. The data transmission circuit includes a clock generation circuit C1 and an output circuit C2. The clock generation circuit C1 generates an internal clock signal InCLK according to an external clock signal ExCLK. The output circuit C2 synchronously outputs data according to the internal clock signal InCLK. The clock generation circuit C1 includes a first CMOS inverter (P1, N1), a second CMOS inverter (P2, N2), a P-channel MOS transistor Qp and an N-channel transistor Qn. The external clock signal ExCLK is input to the first CMOS inverter (P1, N1). The second CMOS inverter (P2, N2) is connected to an output of the first CMOS inverter (P1, N1), and outputs the internal clock signal InCLK. The P-channel MOS transistor Qp is connected between a power Vcc and the transistor P1, and the N-channel transistor Qn is connected between the output of the first CMOS inverter and the ground GND.
A power down signal P/D is applied to gates of the transistors Qp and Qn. The power down signal P/D is in a low logic level (which is represented by a “L” level hereinafter) during an enable state, and is in a high logic level (which is represented by a “H” level hereinafter) during a standby state. The P-channel transistors P1 and P2 used for constructing the first CMOS inverter and the second CMOS inverter are low-threshold transistors.
The output circuit C2 includes a third CMOS inverter (P3, N3), a fourth CMOS inverter (P4, N4), a P-channel transistor P5, an N-channel transistor N5, a P-channel transistor Qp and an N-channel transistor Qn. The internal data is input to the third CMOS inverter (P3, N3). The fourth CMOS inverter (P4, N4) is connected to the output of the third CMOS inverter, and outputs the above internal data. The P-channel transistor P5 and the N-channel transistor N5 are respectively connected in series to the third CMOS inverter. The P-channel transistor Qp is connected between the transistor P5 and the power Vcc, and the N-channel transistor Qn is connected between the output of the third CMOS inverter and the ground GND.
The inverter internal clock signal InCLK is applied to a gate of the transistor P5, and the internal clock signal InCLK is applied to a gate of the transistor N5. The power down signal P/D is applied to gates of the transistors Qp and Qn. The P-channel transistors P3 and P4 used for constructing the third CMOS inverter and the fourth CMOS inverter and the clock synchronous transistor P5 are low-threshold transistors.
During the enable operation, the power down signal P/D is in the logic low (L) level, so that the transistors Qp are in a turn-on state, and the power Vcc is coupled to the first CMOS inverter and the third CMOS inverter, and now the transistors Qn are in a turn-off state. Therefore, the internal clock signal InCLK synchronous to the external clock signal ExCLK is output from the clock generation circuit C1. Moreover, in the output circuit C2, when the internal clock signal InCLK connected to the transistors P5 and N5 has the logic low (L) level, the internal data is obtained by the third CMOS inverter, and the fourth CMOS inverter outputs data with the logic value corresponding to that of the input data.
If the standby state is entered, the power down signal P/D is in the logic high (H) level. Therefore, in the clock generation circuit C1, the transistor Qp is in the turn-off state, and the power voltage Vcc does not provide an operation voltage to the low-threshold transistor P1. Moreover, the transistor Qn is in the turn-on state, so that the internal clock signal InCLK output by the clock generation circuit C1 is fixed to the logic high (H) level. Moreover, in the output circuit C2, the power voltage Vcc does not provide the operation voltage to the transistor P3, and the transistor Qn is in the turn-on state. Therefore, the output data is fixed to the high level.
According to the above descriptions, in order to reduce the leakage currents of the low-threshold transistors P1 and P3, the general-threshold transistors Qp and Qn have to be connected in series, and have to be logically set according to the power down signal P/D. In this way, the low-threshold transistors P1 and P3 can be used to implement high-speed operation. However, since the transistors Qp and Qn are connected in series, channel widths of the transistor P1, the transistor Qp and the transistor P3, the transistor Qp are increased, so that in order to set the standby state, the logic portion has to be increased. Moreover, in the standby state, since the output data is fixed to the high level, when the standby state is changed to the enable state, the logic portion has to be initialised, which takes more time for implementation.